Sequential logic functions, sequential nature of the behavior, feedback, sequential and temporal logic elements, synchronous and asynchronous execution
Synchronous and asynchronous execution

## Asynchronous flip-member

Asynchronous flip-flop is not controlled by any time signal and its status can be changed at any time by changing the input signal.

Basic asynchronous flip-flop circuit is a "RS" project gates "NAND" labeling scheme is shown in Figure 5.6 Logic is a wiring diagram in Figure 5.5.

Fig. 5.5: Pictogram
Fig. 5.6: Realization NAND gate

If the perimeter of the "RS" project gates "NOR" labeling scheme is shown in Figure 5.7. Logic is a wiring diagram in Figure 5.8. These circuits have one indeterminate state.

Fig. 5.7: Pictogram
Fig. 5.8: Realization by NORs

Other flip-flops are circuits of type "SL" (set, latch - blocking) or "EL" (erase - delete, latch). These districts have banned or indeterminate states. Schematic symbol and logical connection SL-type flip-flop is shown in Figure 5.9. Schematic symbol and logical connection SL-type flip-flop is shown in Figure 5.10.

Fig. 5.9: Trigger circuit SL

Table 8: Logical table for trigger circuit SL
S | L | Q |
0 | 0 | PREVIOUS STATE
0 | 1 | 0 | 1
1 | 0 | 1 | 0
1 | 1 | 1 | 0

Fig. 5.10: Trigger circuit EL

Table 9: Logical table for trigger circuit EL
E | L | Q |
0 | 0 | PREVIOUS STATE
0 | 1 | 0 | 1
1 | 0 | 1 | 0
1 | 1 | 0 | 1

## Synchronous flip-member

In everyday life, it is possible to meet two kinds of sequence control. For example, the protection of man at the entrance to the working space robot and ensure safe entry into the road at a pedestrian light controlled crossing. In the first case there is an immediate cessation of movement of the robot. In the second case, after pressing the button, the first people to clear the road and then to indicate safe crossing for pedestrians. In the first case, it is necessary to use asynchronous flip-member, it means instant response to changing conditions. In the latter case, the use synchronous tilting member. It is a member that is activated in addition to changes in the input values have a time input. For time input is applied rectangular pulse. To change the output can then use rising or falling edge of the pulse.

Inputs to the synchronous flip-flop is three and labeled "J", "K" and "C" (clock - input clock pulse). The outputs are again coplanar (mutually opposite) labeled "Q" and " ". Schematic symbol and logical table corresponding to control rising edge of the clock input is given in Table 5.4. The time course of the output signal in response to changes in inputs in Figure 5.12 Figure 5.13. is plotted logic controlled synchronous flip-member rising edge.

Fig. 5.11: Trigger circuit JK, output signal in time

Table 10: Logical table for trigger circuit JK
C | J | K | Q |
| 0 | 0 | PREVIOUS STATE
| 0 | 1 | 0 | 1
| 1 | 0 | 1 | 0
| 1 | 1 | NEG. PREVIOUS

Fig. 5.12: Output signal in time
Fig. 5.13: Logical scheme for JK circuit